Design of Memory Encryption for RISC-V CPU

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dc.contributor.advisorFitsum Asamnew (PhD)
dc.contributor.advisorSalessawi Ferede (PhD)
dc.contributor.authorHaimanot Tizazu
dc.date.accessioned2025-12-31T09:46:45Z
dc.date.available2025-12-31T09:46:45Z
dc.date.issued2025-06
dc.description.abstractThe increasing demand for secure computing in embedded and general-purpose systems has heightened the importance of hardware-based memory protection mechanisms. This thesis investigates the design and implementation of memory encryption techniques tailored for RISC-V processors, with a focus on architectural design choices and performance trade-offs. This work proposes a lightweight Memory Encryption Unit (MEU) integrated into the memory controller of a RISC-V architecture to ensure the confidentiality of external memory transactions. The MEU is designed to handle six lightweight encryption algorithms: block ciphers (QARMA, PRINCE, SIMON) and stream ciphers (ChaCha,Grain,Trivium), selected for their low latency and hardware efficiency. By embedding the encryption engines directly within the memory controller, the system performs inline encryption and decryption with minimal performance overhead. The design is implemented and tested on Xilinx Arty-7 FPGAs, enabling detailed evaluation across key metrics including throughput, area utilization, throughput-to-area ratio (TP/A), power consumption, and energy efficiency. The memory encryption architecture was seamlessly integrated into the RISC-V system, introducing a modest storage overhead of 1.5%–4% and an execution overhead of 3%–6%, depending on the encryption algorithm. These results demonstrate that lightweight ciphers can effectively secure memory with minimal impact on system performance and resource utilization.
dc.identifier.urihttps://etd.aau.edu.et/handle/123456789/7594
dc.language.isoen_US
dc.publisherAddis Ababa University
dc.subjectRISC-V
dc.subjectlowRISC
dc.subjectRockcore
dc.subjectDRAM
dc.subjectMemory Encryption
dc.subjectMemory Encryption Unit
dc.subjectBlock Cipher
dc.subjectStream Cipher
dc.subjectFPGA.
dc.titleDesign of Memory Encryption for RISC-V CPU
dc.typeThesis

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