Design of Memory Encryption for RISC-V CPU
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Date
2025-06
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Addis Ababa University
Abstract
The increasing demand for secure computing in embedded and general-purpose systems has heightened the importance of hardware-based memory protection mechanisms. This thesis investigates the design and implementation of memory encryption techniques tailored for RISC-V processors, with a focus on architectural design choices and performance trade-offs. This work proposes a lightweight Memory Encryption Unit (MEU) integrated into the memory controller of a RISC-V architecture to ensure the confidentiality of external memory transactions. The MEU is designed to handle six lightweight encryption algorithms: block ciphers (QARMA, PRINCE, SIMON) and stream ciphers (ChaCha,Grain,Trivium), selected for their low latency and hardware efficiency. By embedding the encryption engines directly within the memory controller, the system performs inline encryption and decryption with minimal performance overhead. The design is implemented and tested on Xilinx Arty-7 FPGAs, enabling detailed evaluation across key metrics including throughput, area utilization, throughput-to-area ratio (TP/A), power consumption, and energy efficiency. The memory encryption architecture was seamlessly integrated into the RISC-V system, introducing a modest storage overhead of 1.5%–4% and an execution overhead of 3%–6%, depending on the encryption algorithm. These results demonstrate that lightweight ciphers can effectively secure memory with minimal impact on system performance and resource utilization.
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Keywords
RISC-V, lowRISC, Rockcore, DRAM, Memory Encryption, Memory Encryption Unit, Block Cipher, Stream Cipher, FPGA.