A Modified Tetrolet Based Image De-Noising for Real Time Edge Detectors

dc.contributor.advisorDerebssa, Bisrat (Mr)
dc.contributor.authorTeshome, Eyob
dc.date.accessioned2018-07-11T11:27:34Z
dc.date.accessioned2023-11-04T15:14:38Z
dc.date.available2018-07-11T11:27:34Z
dc.date.available2023-11-04T15:14:38Z
dc.date.issued2012-12
dc.description.abstractImage de-noising involves the manipulation of the image data to produce a visually high quality image. Computer vision involves the identification and classification of objects in an image, therefore edge detection is an essential tool. Aiming at the problems of traditional edge detection algorithms such as Sobel, Prewitt, Canny and LoG etc. on noise immunity, this paper presents a combination of an adaptive image de-noising algorithm based on the Tetrolet transform and first order gradient based edge detectors. An improved image de-noising algorithm based on the Tetrolet wavelet transform is proposed. The Tetrolet transform is an adaptive Haar wavelet transform whose support is Tetrominoes, that is, shapes made by connecting four equal sized squares. The algorithm is proposed to improve de-noising performance for images corrupted by additive white Gaussian noise (AWGN), Poisson noise, and Speckle noise. Which in turn used to improve the first order gradient based edge detection algorithms. The system is simulated in Matlab, and performance is tested on Standard images. The proposed algorithm improves de-noising performance measured in peak signal-to-noise ratio (PSNR) by 1-2.0 dB over the Haar wavelet transform based de-noising algorithms for images corrupted by additive white Gaussian noise (AWGN) assuming universal hard thresholding. The computational time for the software implementation is also significantly improved compared to the previous Tetrolet based image de-noising algorithm. The local nature of the algorithm makes the proposed method well suited for efficient hardware implementation. Preliminary results showed that FPGA design of the discrete forward Tetrolet transform is running at 155.027MHz MHz targeting Virtex-4 FPGA.en_US
dc.description.sponsorshipAddis Ababa Universityen_US
dc.identifier.urihttp://etd.aau.edu.et/handle/123456789/8012
dc.language.isoenen_US
dc.publisherAddis Ababa Universityen_US
dc.subjectMicroelectronics Engineeringen_US
dc.titleA Modified Tetrolet Based Image De-Noising for Real Time Edge Detectorsen_US
dc.typeThesisen_US

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