(7,3) Maximum - Length Binary Cycle Code Applied to Single Channel Digital Communication System for Error Correction
| dc.contributor.advisor | Alemu, Ketema(phD) | |
| dc.contributor.author | snegash, Yohanne | |
| dc.date.accessioned | 2018-07-10T07:17:35Z | |
| dc.date.accessioned | 2023-11-28T14:26:37Z | |
| dc.date.available | 2018-07-10T07:17:35Z | |
| dc.date.available | 2023-11-28T14:26:37Z | |
| dc.date.issued | 1996-06 | |
| dc.description.abstract | This paper presents the design and hardware implementation of the (7,3) maximum-length binary cyclic code applied to a single channel communication system. In hardware implementation of the system a PC with a data acquisition board with time <- sharing for interfacing the analog signals. A 12-bit digital output of the PC is divided into blocks of 3-bits for processing by the channel encoder The implementation of the system is carried out using shift registers and logic gates. A sinusoidal input waveform is applied to the system input and a circuit designed with a combination of D-type flip-flops and logic gates is used to introduce the effects of a single-random-error and a double-adjacent-burst error to observe the performance of the system. The code resulted in good performance in correcting a single-random-error and a double-adjacent-burst-error. | en_US |
| dc.identifier.uri | http://etd.aau.edu.et/handle/12345678/7508 | |
| dc.language.iso | en | en_US |
| dc.publisher | Addis Ababa University | en_US |
| dc.subject | (7,3) Maximum - Length Binary | en_US |
| dc.subject | Cycle Code Applied | en_US |
| dc.title | (7,3) Maximum - Length Binary Cycle Code Applied to Single Channel Digital Communication System for Error Correction | en_US |
| dc.type | Thesis | en_US |