Design of Pulse Width Modulation (Pwm) and It’s Implementation In Xilinx Field Programmable Gate Array (Fpga
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Date
2007-02
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Addis Ababa University
Abstract
The following thesis describes the design, the synthesis, and the implementation of pulse width
modulation (PWM) in Xilinx Field Programmable Gate Array (FPGA). The contribution of this
thesis is the development of PWM in Xilinx Integrated System Environment (ISE) CAD tools
and The VHDL modeling is used in the design process of PWM.
Pulse width modulation has been widely used in many applications especially in communication
and control systems. The paper develops high frequency PWM generator architecture for using
FPGA. The resulting FPGA frequency depends on the target FPGA speed grade and the duty
cycle resolution requirements.
In most industrial application due to the need of design integration in control systems FPGA
based PWM controller is advantageous over the other controller systems like microprocessor,
microcontroller and so on.
As geometries shrink and device counts multiply, opportunities abound to do incredible things
with in the confines of a single chip (FPGA). Greater focus on design reuse, where earlier design
is utilized and reused in later design. The power, compactness and flexibility of the FPGA based
controller could be useful in motor control, particularly in robotics where those qualities are
important. The FPGA provides advantages over traditional methods such as microcontroller
based designs and PLD/ASIC designs by combining the strengths of both. The FPGA allows for
implementation of parallel processing for generating the required waveforms. In addition to this
the paper describes the architectural features of Xilinx FPGA to the other programmable logic
device and explores the design using Very high speed integrated circuit hardware description
language (VHDL). The VHDL model was implemented on the Spartan 3e FPGA and optimized
for space. The optimized implementation was found to consume 34 numbers of slices, 18
numbers of slice flip flops, 65 numbers of 4 input LUTs and 11 numbers of bonded IOBs.
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Keywords
Programmable Gate Array