Browsing by Author "Tekeba, Menore"

Now showing 1 - 4 of 4
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    Ancient Ethiopic Manuscript Recognition Using Deep Learning Artificial Neural Network
    (Addis Ababa University, 2016-03) Getu, Siranesh; Tekeba, Menore
    The recognition of handwritten documents, which aims at transforming written text into machine encoded text, is considered as one of the most challenging problems in the area of pattern recognition and an open research area. Especially ancient manuscripts, like Ethiopic Geez scripts, are different from the modern documents in various ways such as writing style, morphological structure, writing materials and so on. This brings the necessity to make research works on characetr recogntion of those scripts. Geez is one of the ancient languages which has been used as a liturgical language in Ethiopia. Manuscripts written using this language contains many unexplored content which is the base of the current Ethiopic scripts; however, only few researches have been done on these valuable documents. A number of algorithms have been proposed for handwritten character recognition such as support vector machine, hidden Markov model, and neural network. In this research the design and implementation of character recognition system for ancient Ethiopic manuscript using deep neural network is presented. Deep learning, is employed and trained using a Restricted Boltzman Machine (RBM), a greedy layer-wise unsupervised training strategy. The complete system employs image acquisition, preprocessing, character segmentation, and classification and recognition. Efficient and effective algorithms were selected and implemented in each step. A dataset was also prepared to train and test the system, which consists of 24 base characters of Geez alphabet with 100 frequencies. Overall, a recognition accuracy of 93.75 percent was obtained using 3 hidden layers with 300 neurons. Analysis of results obtained i from each step of the recognition process shows that the system can be extended and fine-tuned for practical application. Key words: Ancient Ethiopic Manuscript, Handwritten Recognition, Preprocessing, segmentation, Deep Neural Network, Restricted Boltzmann Machine.
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    A General Pyramidal Modular Neural Network Architecture for High Dimensional Input Vectors
    (Addis Ababa University, 2011-09) Tekeba, Menore; Raimond, Kumudha (PhD)
    In this thesis new modular neural network (MNN) architecture is proposed. The basic building blocks of the architecture are small multilayer feed forward networks trained using the Back propagation algorithm (BPA). The newly proposed MNN Architecture is called Pyramidal MNN (PMNN). It is called Pyramidal for the number of the modules that constitutes the layers of network relatively decreases from the input layer to the output layer. An Optimization technique called PSO has been used to optimize the topology of the proposed PMNN architecture for typical high dimensional input vector datasets. The optimization technique is used to suit the PMNN architecture for specific problems of high dimensional input vectors depending on the nature of the data input and the nature of the problem. This is done by evolving topology of the modules that constitutes the network and changing the architecture of the overall network to suit the new data set. The suggested training algorithm works in multiple stages depending on the number of hidden layers of the network. The training of modules in the same layer of the PMNN is easy to implement in parallel. Since the network is not fully connected, the number of weight of connections is less and hence the training is very quick for large input dimensional vectors. An object-oriented implementation of the proposed PMNN architecture is written to simulate the behavior. The evaluation and optimization of the PMNN architecture for different real world applications is carried out to show the effectiveness of the proposed architecture for high dimensional input vector applications. The evaluation is based on three pattern recognition problems: palm-print recognition, iris recognition and face recognition. In all the three evaluations, it has achieved more than 95% accuracy of the test results. Furthermore, the proposed PMNN architecture performs better than other similar type research works. It is shown that as PMNN is a huge family of several specific architectures, this proposed topology of the neural net can serve wide range of complex domain problems that need to be solved using Artificial Intelligence (AI). Keywords: Modular Neural Networks, Pyramidal Modular Neural Networks, Particle Swarm Optimization, High Dimensional Input Vectors, General Pyramidal Modular Neural Networks,
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    Identification of High-Risk Hardware Path-Delay Fault Locations and Evaluation of Their Impact
    (Addis Ababa University, 2014-09) Basazenew, Tadele; Tekeba, Menore
    Ascertaining correct operation of digital logic circuits requires verification of functional behavior as well as correct operation at desired clock speed. The maximum allowable clock rate in a digital circuit is determined by the propagation delays of the combinational logic network between latches. If the delay of the manufactured network exceeds specifications due to some physical defects or process variations, non-confidential and possibly incorrect logic values may be latched in memory elements. In this thesis, we present novel and efficient model for path delay faults specifically for stack at fault in combinational logic circuits. We propose new and efficient Model for delay fault analysis, test generation and fault simulation of path delay faults in combinational logic circuits. Then the new model was analyzed using reduced order binary decision diagram of the Colorado University Decision Diagram package. An approach for selecting critical paths along which testable path delay faults can exist is presented. The proposed method is particularly helpful on path intensive circuits (large number of paths). Critical paths are selected implicitly with the aid of a combination of decision diagrams. Ideally, all the path delay faults of a circuit should be tested. However, a circuit may have a very large number of paths, making it impossible to target all the path delay faults explicitly during test generation or fault simulation. The large numbers of paths in practical circuits lead to the use of path selection, where only subsets of the path delay faults in circuits are targeted for test generation, in this case only high-risk paths. To reduce our efforts for finding test vectors, which in turn reduce testing memory and processor power and analyzing a circuit for its faults, we try to use reduced faults. Reduced faults can be obtained by eliminating redundant ones and ignoring some that do not occur often or by eliminating faults that have the same output effect by fault collapsing rules.The effectiveness of the approach is demonstrated on path intensive international symposium on circuits and systems (ISCAS'85) and International Transmission Company (ITC'99) benchmarks. Keywords:-High-risk Paths, Delay Fault Model, ROBDD, Fault reduction
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    Reliable Data Transmission and Energy Efficient Sleep Scheduling for Mult-Source Multi-Sink Wireless Sensor Networks
    (Addis Ababa University, 2014) Tamir, Kassahun; Tekeba, Menore
    Multi-source multi-sink wireless sensor networks (WSNs) have got variety of application in areas that need to detect multiple environmental monitored parameters using a single sensor field/network. This type of WSN, beside its limited resources such as energy limitation like any WSNs are, has unique characteristics for instance network congestion, since multiple sensor nodes can send data to multiple/single sink at the same time. Research works on WSNs are not matured and well-developed. There are a number of research issues that are not yet addressed. In particular reliable data transmission and energy efficiency of WSNs are among those that are the decisive and unsolved ones as much as required. So energy efficiency is increased for multi-source multi-sink type WSNs without affecting a 100% reliable data transmission. In this thesis work, reliable data transmission is ensured by employing hop-by-hop (in every hop) loss detection and recovery. Much energy lost due to idle listening is solved using pre-scheduling i.e. sleep and active periods of nodes are pre-scheduled. These ideas are implemented using Network Simulator (NS-2) simulator. The simulation and experimental results show that the new protocols perform well under various conditions and protocol parameter settings. This paper provides 100% reliable data transmission and reduces the energy nearly by 50% that can be wasted by IEEE 802.11. Reliability is assured by employing hop-by-hop loss detection and recovery using a hybrid of NACK and ACK-based approach. Since NACK-based scheme cannot handle the unique case where all packets in a communication are lost, we used a last single ACK feedback to make the sender sure that all packets are received successfully. We can save more energy by employing SMAC; however, the network performance such as throughput and latency of SMAC is very poor. But in this thesis work energy saving is next to reliability and network performance. Keywords: energy efficient sleep scheduling, idle listening, multi-source multi-sink wireless sensor networks, reliable data transmission, wireless sensor networks