Microelectronics Engineering

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Browsing Microelectronics Engineering by Author "Daniel, Dilbie (Mr.)"

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    Design and Simulation of Front End 3-in-1 EEG, ECG, EMG Bio-Potential Signal Acquisition System
    (Addis Ababa University, 2020-06) Yonas, Worede; Daniel, Dilbie (Mr.)
    The last couple of years have given birth to meticulously mapped and innovative solutions in regards to product as well as research of medical analysis tools and diagnostic equipment. The industry has shown a major transformation on the general process of diagnosis tools providing flexibility and enhanced accuracy. However, despite the astonishing progress of the bio-medical industry, the status of medical provision is still a concern in third world countries. The inaccessibility and unaffordability of medical equipment in such countries needs immediate attention as many people fall prey to this problem which can be solved through the provision of a supplementary solution that can aid the process of preliminary diagnosis. In this thesis, the design of a front-end system for EEG, ECG and EMG signal acquisition is done. The design addresses the problem of medical provision in under developed nations by providing a supplementary hardware that is portable making it cost-efficient and readily available. Moreover, it extends the research aspect in the area through the combination of a 3-in-1 signal acquisition hardware and optimizing the design in regards to performance, complexity and scalability. Owing to the fact that the signals operated by the hardware are very weak in nature, the utilization of low noise amplifiers with very high common-mode rejection ratio and gain adjustment is critical. Moreover, the implementation of analog-to-digital conversion needs a thorough analysis in regards to the architecture, resolution and area of application. Accordingly, the design in this thesis is specifically done so as to improve the performance in regards to noise cancellation, minimization of filter circuitry, number of channels and overall circuit complexity. Verification of the design is done with the co-simulation of PSPICE and SIMULINK. The simulation is carried out for individual cases of EEG, EMG and ECG application by using physiological signals of patients from PhysioNet.org through the addition of noise signals to mimic actual physical application of the hardware. Furthermore, the output is analyzed and compared with existing products and previous researches in the area which yielded a 21% improvement in common-mode rejection ratio and a 33% increase in channel capacity.
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    Design of an Improved ADPLL For Dual Band GSM
    (Addis Ababa University, 2013-02) Gosa, Demissie; Daniel, Dilbie (Mr.)
    All Digital Phase Locked Loop are widely used frequency synthesizers in different radio communication systems. To use analog phase locked loop in different processes is difficult due to its process sensitivity. In conventional all digital phase locked loop all blocks are defined to be digital at both input and output level. In normal all digital phase locked loop the analog parts degrade the performance of the whole system related to frequency of operation. The new ADPLL architecture, which is the digital counter part of conventional CPPLL, is designed by discritizing conventional charge pump phase locked loop. It is designed using digital blocks in the new architecture, isolation rings and bulky loop filter components are replaced, and hence the system can become area efficient, consumes less power and low jitter. The digital block used in the design in place of analog charge pump help the application to be free of analog charge pump pitfalls like charge pump mismatch, leakage, thermal noise, aging and drift. Moreover, using the new architecture the system is made stable and hence more portable and robust operation. Higher rate clocks and huge processing time problems at the controller end is reduced using digital block used in the architecture. In a nutshell the design of integrated circuit is targeted for 900 MHz and 1800 MHz center frequencies with tuning range of 200 MHz and is done in UMC 130 nm technology. It consumes an average current of 13mA and applicable for 1.2V supply voltage. The chip area is less than 0.12mm2 and the average settling time is 3.55 usec.