Design of an Improved ADPLL For Dual Band GSM
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Date
2013-02
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Addis Ababa University
Abstract
All Digital Phase Locked Loop are widely used frequency synthesizers in different radio communication systems. To use analog phase locked loop in different processes is difficult due to its process sensitivity. In conventional all digital phase locked loop all blocks are defined to be digital at both input and output level. In normal all digital phase locked loop the analog parts degrade the performance of the whole system related to frequency of operation.
The new ADPLL architecture, which is the digital counter part of conventional CPPLL, is designed by discritizing conventional charge pump phase locked loop. It is designed using digital blocks in the new architecture, isolation rings and bulky loop filter components are replaced, and hence the system can become area efficient, consumes less power and low jitter. The digital block used in the design in place of analog charge pump help the application to be free of analog charge pump pitfalls like charge pump mismatch, leakage, thermal noise, aging and drift. Moreover, using the new architecture the system is made stable and hence more portable and robust operation. Higher rate clocks and huge processing time problems at the controller end is reduced using digital block used in the architecture.
In a nutshell the design of integrated circuit is targeted for 900 MHz and 1800 MHz center frequencies with tuning range of 200 MHz and is done in UMC 130 nm technology. It consumes an average current of 13mA and applicable for 1.2V supply voltage. The chip area is less than 0.12mm2 and the average settling time is 3.55 usec.
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Keywords
Charge pump phase locked loop, All digital phase Locked loop, discritization technique, dual-band GSM, new architecture, digitally controlled oscillator