FPGA Based Optimum-Settling Automatic Gain Control Circuit Design for Multistage Amplification

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Date

2018-03

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Addis Ababa University

Abstract

Many electronic applications require their input signal to be of constant amplitude. Especially, in communication systems, the transmitted signal may be faded and the amplitude of the received signal may be below the desired level due to multi-path fading and different positions. This thesis work solves problems of inconsistent amplitude signal arrival at receiving sides of electronic systems. Automatic Gain Control (AGC) circuits are mainly used in such applications to adjust the gain of a Variable Gain Amplifier (VGA) and to provide relatively constant amplitude signal to the receivers. This work makes use of multi-stage amplification circuits to increase the dynamic range of the AGC. Three amplification stages are designed which increased the gain from 21 dB in single stage to 63 dB in three stages. Due to their flexibility better than ASICs as well as high performance speed and better power efficiency than microcontrollers, FPGAs are preferred in modern high speed technologies. Consequently, this thesis work used FPGAs to generate control voltages to adjust the gain of VGAs in the multistage amplification circuit. The designed AGC employs both feedback and feedforward loops to optimize the settling time. Feedback loop is used in input stage and feedforward loop is used in intermediate and output stages. When the amplitude level of the input signal diverges from the desired level, the FPGA generates a control voltage that adjusts the gain of the VGA and the result is an output signal with consistent amplitude level. A reference input of 25 mVpeak is considered and the AGC circuit is tested with input signals of amplitude below and above the chosen reference value. For all tested inputs a constant amplitude signal of 87 mVpeak is achieved.

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Keywords

AGC, FPGA, VGA, feedback, feedforward, multistage, amplification

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