Design of 3D Graphics Accelerator Core for FPGA
| dc.contributor.advisor | Alemu, Getachew (PhD) | |
| dc.contributor.author | Abebe, Kibret | |
| dc.date.accessioned | 2018-07-11T11:41:21Z | |
| dc.date.accessioned | 2023-11-04T15:14:38Z | |
| dc.date.available | 2018-07-11T11:41:21Z | |
| dc.date.available | 2023-11-04T15:14:38Z | |
| dc.date.issued | 2011-10 | |
| dc.description.abstract | In this thesis we designed and synthesized 3D graphics accelerator Intellectual Property (IP) using VHDL. The main parts which were designed in this work include: the geometry unit and the rasterizer unit of 3D graphics pipeline. The geometry unit design contains two main parts , the matrix transformation unit and clipping unit. The rasterzer unit based on bresenham line drawing algorithm. By doing this state-of-the-art design methodology divided in two sections, the first section is used to describe each block (i.e the matrix multiplier, matrix transformer , clipping and rasterizer) of the pipeline using VHDL and simulate each unit behaviorally. Second part synthesizes the system using Xilinx ISE 13.1 tool on XUP5VLX110T-1F1136. After doing the synthesis the designed 3D graphics accelerator performance was found to be 100M pixel fill rate with maximum clock frequency of 169 MHz. | en_US |
| dc.description.sponsorship | Addis Ababa University | en_US |
| dc.identifier.uri | http://etd.aau.edu.et/handle/123456789/8024 | |
| dc.language.iso | en | en_US |
| dc.publisher | Addis Ababa University | en_US |
| dc.subject | Computer Engineering | en_US |
| dc.title | Design of 3D Graphics Accelerator Core for FPGA | en_US |
| dc.type | Thesis | en_US |