High Throughput Aes Crypto Co-Processor

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In 2001, National Institute of Standards and Technology (NIST) approved Rijndael as Advanced Encryption Standard(AES).Since its approval, AES is being used widely in different security applications for its good security, simple design and hardware suitability.AES can be used to encrypt any digital information including videos, images and texts.Since the algorithm involves several iterations, there is still a challenge for high performance implementation.There are some cryptographic applications which demand a higher data throughput implementation of the algorithm.Many researches were done on improving its performance for specific application. In this thesis ,we presented a higher data throughput implementation of AES 128 bit encryption module for FPGA technology than the previous works in the litrature.We started by exploring different available architectures for high throughput design.Then ,FPGA specific features were studied and incorporated in the implementation to improve the throughput of the algorithm.A fully unrolled and pipelined architecture together with pre calculated and stored key values for each rounds is used.We have used VHDL as a hardware description language.The software used for this work is Xilinx ISE design suite 12.3.This tool is used for writing, debugging and also for Synthesis Place and Route. Simulation and checking the performance results were done using the simulation tool ISim Simulator available with the software.From the synthesis result we obtained ,the system runs at 450.532MHz and has a throughput of 57.668 Gbps.



Computer Engineering