Neural Network Based Processing Architecture on Intel Cyclone V SoC 5CSEMA5F31C6 for Amharic Handwriting Recognition
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Date
2025-09
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Addis Ababa University
Abstract
Due to the physical limitations of continued growth predicted by Moore's Law many researchers are seeking new avenues through hardware/software co-design structures to further increase their computer performance. This Thesis proposes New Hardware Architectures that utilize custom hardware to provide Best performance for Deep Learning Applications. More specifically this case study will test these hardware architectures on a specific application the analysis of Amharic handwriting characters through a created database developed from an Amharic handwriting text source that has been created through both Image Processing and Labelling Techniques to be used to effectively train a Neural Network. In order to Facilitate a Bridge between becoming an effective software prototype and developing fast hardware accelerators a full Verilog implementation of a scalable design optimised for the Cyclone V SoC will be created, using fixed Point Arithmetic, Block RAM (BRAM) and Pipe lined Neuron Design structures; additionally, the Hardware Design of the Custom Chip will require the use of techniques including Model Compression & Quantization to manage the different trade-offs involved between throughput, Latency, Power Consumption and Memory Footprint. In addition to enabling the efficient creation of Amharic Character Recognition Solutions using Custom Hardware Design for Neural Networks, this Hardware Architecture will allow the flexible ability to perform both Training and Inference Tasks on the same piece of Hardware. By giving device Designer's the ability to integrate Machine Learning Frameworks with their FPGA & SoC Customisation efforts, this work is expected to lead to further development of Custom, Energy Efficient Domain-Specific Computing Architectures capable of providing longer-term Performance Improvements that extend beyond the existing limits of Moore's Law.
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Keywords
Neural networks, Intel Cyclone V SoC 5CSEMA5F31C6, hardware architecture, Amharic handwriting recognition, Moore’s Law, model compression