Hardware Acceleration of Elliptic Curve Based Cryptographic Algorithms: Design and Simulation
| dc.contributor.advisor | V.N.V, Manoj (PhD) | |
| dc.contributor.author | Kedir, Mubarek | |
| dc.date.accessioned | 2018-06-28T12:07:37Z | |
| dc.date.accessioned | 2023-11-04T15:14:33Z | |
| dc.date.available | 2018-06-28T12:07:37Z | |
| dc.date.available | 2023-11-04T15:14:33Z | |
| dc.date.issued | 2008-04 | |
| dc.description.abstract | Elliptic curve cryptography (ECC) is an alternative to traditional public key cryptographic systems. Even though, RSA (Rivest-Shamir-Adleman) was the most prominent cryptographic scheme, it is being replaced by ECC in many systems. This is due to the fact that ECC gives higher security with shorter bit length than RSA. In Elliptic curve based algorithms elliptic curve point multiplication is the most computationally intensive operation. Therefore implementing point multiplication using hardware makes ECC more attractive for high performance servers and small devices. In this thesis FPGA accelerator for point multiplication over GF (2163) is proposed. We designed and synthesized the point accelerator using Xilinx XCV2000 FPGA. Binary field arithmetic units from which the point accelerator is built are also designed and synthesized. Experimental results show that a single point multiplication executes in 47μs. This is a 161 fold speed up over software implementation. And it is also better than the fastest hardware accelerator published in the literature | en_US |
| dc.identifier.uri | http://etd.aau.edu.et/handle/123456789/4664 | |
| dc.language.iso | en | en_US |
| dc.publisher | Addis Ababa University | en_US |
| dc.subject | Algorithms | en_US |
| dc.title | Hardware Acceleration of Elliptic Curve Based Cryptographic Algorithms: Design and Simulation | en_US |
| dc.type | Thesis | en_US |