Design of Safety-Critical Wayside Train Control System
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Date
2014-08
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Addis Ababa University
Abstract
Due to the difficulty to analyze all failure modes of complex microprocessor based systems, it is risky to use those devices for a safety-critical Automatic Train Control system. A means to guarantee safety is a must in a microprocessor based train control systems. In this paper, the design and implementation of a safety-critical computing platform for real-time automatic train control system is presented. The input, output and interlocking logic controller module emulators are designed and implemented in software for the prototype based on a simplex processing configuration and its associated safety assurance scheme. The safety assurance method used is based on information redundancy which detects errors arising from faults in the software and hardware of the control system. A prototyping environment is also developed as an experimental test bed for design and performance evaluation of the system. Noisy random, data reference, symbol creation and timing errors were injected to the system to evaluate its performance. For the different classes of errors, the prototype control system provided safe decision to the railway plant. The results obtained indicate that the use of a simplex coded processor for the prototype control system was indeed reasonable to enforce safety. It was difficult to properly gauge the performance of the architecture with the current implementation, since it was implemented in software to provide a proof-of-concept to the adopted architecture. However, it serves as a solid foundation from which to develop future prototype designs. The prototype design represents an initial version of an architecture that is evolving from the wayside application to more advanced systems. Several design iterations are required to support advanced system functionality.
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Keywords
Interlocking, Microprocessor, Safety-critical applications, Wayside train control, Input module, Output module, Interlocking logic controller module, ATC, Simplex processing, Information redundancy