Development of FPGA Based System on Chip for Level Crossing Management System in Case Of AALRT
| dc.contributor.advisor | Yalemzewd, Negash (PhD) | |
| dc.contributor.author | Solomon, Hailemichael | |
| dc.date.accessioned | 2019-06-26T04:11:05Z | |
| dc.date.accessioned | 2023-11-04T15:17:03Z | |
| dc.date.available | 2019-06-26T04:11:05Z | |
| dc.date.available | 2023-11-04T15:17:03Z | |
| dc.date.issued | 2015-05-14 | |
| dc.description.abstract | The purpose of this thesis is to develop an automatic railway gate system that uses the FPGA as a main function of design. The principle objective of this thesis was to design an automatic railway gate control by FPGA. This thesis deals to develop a prototype of railway gate that function automatically by using FPGA. Besides that, the interfacing program also had been developed for the integration part. The main concept of the system is that, depending on arrival or departure of the train near level crossing, the crossing gate will close or open automatically with displaying corresponding signals like Red or Green signal. That means, when the train approaching near level crossing, the crossing gate will close and showing Green signal for train, so, train can move without any interruption of its speed. After leaving the train from level crossing, the crossing gate will open, but there may be a chance that when a vehicle is trying to cross the level crossing then the crossing gate may close as the train is approaching nearby. At this situation, the system detects the vehicle as an obstacle in order to prevent accidents, so the gate will be opened until the vehicle moves away from the crossing gate and the train will be stopped as it detects the Vehicle as obstacle just under crossing gate. By developing automatic gate control, the railway level crossing accidents of Ethiopia can be minimized. The system is designed using RF Transceiver, IR Sensor, FPGA, Steeper Motor, Relay and some external devices. | en_US |
| dc.identifier.uri | http://etd.aau.edu.et/handle/123456789/18605 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | Addis Ababa University | en_US |
| dc.subject | Level crossing | en_US |
| dc.subject | FPGA | en_US |
| dc.subject | LabVIEW | en_US |
| dc.subject | Automatic gate control | en_US |
| dc.title | Development of FPGA Based System on Chip for Level Crossing Management System in Case Of AALRT | en_US |
| dc.type | Thesis | en_US |