Computer Engineering

Permanent URI for this collection

http://etd.aau.edu.et/handle/123456789/48

Browse

Browsing Computer Engineering by Author "Adeyabeba, Abera (PhD)"

Now showing 1 - 2 of 2
  • No Thumbnail Available
    Item
    Carbon Nanotube Field Effect Transistors Based RAM Design And Hardware Description Language Code Development
    (Addis Ababa University, 2011-08) Gebremedhin, Mengisteab; Adeyabeba, Abera (PhD)
    The goal of this thesis is to develop carbon nanotube field effect transistors (CNFETs) based static random-access memory (SRAM) and implement it into a Very-highspeed integrated circuit Hardware Description Language Analog and Mixed-Signal (VHDLAMS). To achieve this objective, a compact model of the transistor known as enhancementmode MOSFET-like SWCNT-CNFET is used. This circuit-compatible model of CNFET is described using VHDL-AMS and tested for basic electrical characteristics. This model is valid for CNFETs with channel lengths greater than 20 nm. Based on the CNFETs a new SRAM is designed, and implemented in VHDL-AMS. The performance of the proposed SRAM cell is investigated and compared with SRAMs from conventional metal-oxide semiconductor field effect transistors (MOSFETs). The effect of substrate biasing a CNFET is also demonstrated and implemented in designing the SRAM cell. The VHDL-AMS codes of the CNFET and the SRAM are simulated in software known as Ansoft Simplorer. The compact model of the CNFET is organized hierarchically in three main levels. The first level models the intrinsic channel just beneath the gate of the transistor. The second level builds upon the first level and models the doped source and drain regions of the CNFET. The last level represents the complete trans-capacitance model of the transistor and accounts for multiple CNTs. The proposed SRAM cell is composed of four CNFETs and two load resistors. The driver CNFETs of the proposed SRAM cell are substrate biased. Besides, 8-bit complete SRAM architecture based on this cell is indicated. The performance analysis of the SRAM shows that it has better writing and reading speed as well as better stability when compared with SRAM from conventional MOSFETs. Specifically, the newly proposed SRAM cell has read time of twenty five pico seconds, write time of twenty pico seconds and can tolerate a noise of 120 mV at 32 nm node technology.
  • No Thumbnail Available
    Item
    Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS
    (Addis Ababa University, 2011-07) Teferi, Demisew; Adeyabeba, Abera (PhD)
    The objective of this thesis is to study the basic electronic properties of carbon nanotubes (CNTs here after) and to model the I-V characteristics of metal-oxide-semiconductor field-effect transistor like carbon nanotube field effect transistor (MOSFET-like CNTFET). And finally validate the model by constructing circuits. Electronic properties such as energy band structure, density of state, carrier density, carrier velocity and effective mass are investigated. A complete analytical model of MOSFET-like CNTFET is developed and it was validated by construction of circuits. MOSFET-like CNTFET is chosen because of their relative unipolar property. The model developed is based on analytical calculation of channel potential using electrostatic capacitance and quantum capacitance. Electron phonon scattering effect, band to band tunneling effect (BTBT), source/drain doped region resistance and contact resistance effects are considered in this model. The model requires neither iteration nor numeric integration, hence suitable for hardware description language (HDL) implementation. The model was implemented in VHDL-AMS. Parameters such as gate insulator thickness, gate insulator dielectric constant, CNT diameter, channel length and temperature are examined to observe the performance dependency. Results showed that reducing insulator thickness and increasing dielectric constant improve performance with no compromise other than cost. Channel length scaling increases on-current and also increases off-current, for high bias voltage due to BTBT effect. In addition, the effect of temperature on performance of MOSFET-like CNTFET and the dependency of threshold voltage on diameter of CNT was observed. Finally, using the VHDL-AMS model, circuits were constructed. Resistive-Load inverter, CMOS inverter, and phase shift oscillator circuits are constructed, simulated, and analyzed.