Computer Engineering

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Design of 3D Graphics Accelerator Core for FPGA
(Addis Ababa University, 2011-10) Abebe, Kibret; Alemu, Getachew (PhD)
In this thesis we designed and synthesized 3D graphics accelerator Intellectual Property (IP) using VHDL. The main parts which were designed in this work include: the geometry unit and the rasterizer unit of 3D graphics pipeline. The geometry unit design contains two main parts , the matrix transformation unit and clipping unit. The rasterzer unit based on bresenham line drawing algorithm. By doing this state-of-the-art design methodology divided in two sections, the first section is used to describe each block (i.e the matrix multiplier, matrix transformer , clipping and rasterizer) of the pipeline using VHDL and simulate each unit behaviorally. Second part synthesizes the system using Xilinx ISE 13.1 tool on XUP5VLX110T-1F1136. After doing the synthesis the designed 3D graphics accelerator performance was found to be 100M pixel fill rate with maximum clock frequency of 169 MHz.