Abstract:
This paper presents the design and hardware implementation of the (7,3)
maximum-length binary cyclic code applied to a single channel communication system.
In hardware implementation of the system a PC with a data acquisition board with time
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sharing for interfacing the analog signals. A 12-bit digital output of the PC is divided
into blocks of 3-bits for processing by the channel encoder
The implementation of the system is carried out using shift registers and logic
gates. A sinusoidal input waveform is applied to the system input and a circuit designed
with a combination of D-type flip-flops and logic gates is used to introduce the effects of
a single-random-error and a double-adjacent-burst error to observe the performance of
the system. The code resulted in good performance in correcting a single-random-error
and a double-adjacent-burst-error.