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|Title: ||DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Carbon Nanotube Field Effect Transistors Based RAM Design and Hardware Description Language Code Development|
|Authors: ||Mengisteab, Gebremedhin|
|Advisors: ||Dr. Adeyabeba Abera|
|Copyright: ||Aug-2011 |
|Date Added: ||6-May-2012 |
The goal of this thesis is to develop carbon nanotube field effect transistors
(CNFETs) based static random-access memory (SRAM) and implement it into a Very-highspeed
integrated circuit Hardware Description Language Analog and Mixed-Signal (VHDLAMS).
To achieve this objective, a compact model of the transistor known as enhancementmode
MOSFET-like SWCNT-CNFET is used. This circuit-compatible model of CNFET is
described using VHDL-AMS and tested for basic electrical characteristics. This model is
valid for CNFETs with channel lengths greater than 20 nm. Based on the CNFETs a new
SRAM is designed, and implemented in VHDL-AMS. The performance of the proposed
SRAM cell is investigated and compared with SRAMs from conventional metal-oxide
semiconductor field effect transistors (MOSFETs). The effect of substrate biasing a CNFET
is also demonstrated and implemented in designing the SRAM cell. The VHDL-AMS codes
of the CNFET and the SRAM are simulated in software known as Ansoft Simplorer.
The compact model of the CNFET is organized hierarchically in three main levels.
The first level models the intrinsic channel just beneath the gate of the transistor. The
second level builds upon the first level and models the doped source and drain regions of
the CNFET. The last level represents the complete trans-capacitance model of the transistor
and accounts for multiple CNTs.
The proposed SRAM cell is composed of four CNFETs and two load resistors. The
driver CNFETs of the proposed SRAM cell are substrate biased. Besides, 8-bit complete
SRAM architecture based on this cell is indicated. The performance analysis of the SRAM
shows that it has better writing and reading speed as well as better stability when compared
with SRAM from conventional MOSFETs. Specifically, the newly proposed SRAM cell
has read time of twenty five pico seconds, write time of twenty pico seconds and can
tolerate a noise of 120 mV at 32 nm node technology.|
|Appears in:||Thesis - Electrical Engineering|
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